E-Risc's Home Page

Hi, This is the E-Risc Home Page. Still very much under construction, but you know what it is like when you have just moved in.

The E-Risc is a project to design and implement a scaleable RISC microprocessor for embedded applications. The architecture and all source code are to be released under the GNU General Public Licence (or a slightly modified version that include hardware not just software TBD).

Project Aims
E-Risc Architecture
Instruction Set
Assembler
Instructions Set Simulator
VHDL/Verilog Source

If you would like to discuss any of this send us an Email.

Just a few Links that may be of interest and some background.

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