LAKSHMANAN BALASUBRAMANIAN URL: http://uk.geocities.com/blakshya/index_cv.html Email: lakshmanan@ieee.org Celestijnenlaan 3/61, 3001 Heverlee, Belgium. Mobile: +32-473-445472 Phone (current): +32-16-297598 Phone (permanent): +91-4172-232235 Biography: I received B.Sc degree in Physics from the University of Madras, India in 1995; B.Tech degree in Electronics Engineering from Madras Institute of Technology, Anna University, India in 1998 and M.Tech degree in Electronics Design and Technology from Indian Institute of Science in 2000. My B.Tech and M.Tech theses projects were on Implementation of FPGA based GPS baseband processor and Active noise reduction in pilot's headset respectively and were sponsored by ISRO (Indian Space Research Organisation) and DEBEL (Defence Bioengineering and Electrochemical Laboratory), India respectively. I worked as an IC design engineer with the DSP Product Development Center of Texas Instruments India Ltd. between 2000-2001. During that period I worked on Design for Testability and ATPG for TI's DSP and broadband communication ICs. Since 2001, I have been a research specialist jointly with Interuniversity Microelectronics Center (IMEC), Belgium and the Department of Electrotechniek, Katholieke Universiteit of Leuven (KUL), Belgium. My current research is on Analysis and design techniques for reduced switching noise in mixed signal ICs and low power design. My areas of interest include substrate noise coupling analysis in mixed signal ICs, low power circuit design, signal integrity, mixed signal design, high speed digital design and design for testability. I have been associated with IEEE and IEE since 1998. I am an MIEE and Member, IEEE since 2003. I have been a CEng with Engineering Council of UK since Dec 2000. I was a recipient of NCC National Cadet Welfare Society Scholarship, 1994 and Tamilnadu Government Scholarship for outstanding NCC cadets, 1994. Recipient of Top 1% in the state (Tamilnadu) award in National Graduate Physics Examination -1995 conducted by National Physics Teacher's Association (IAPT). I secured university 3rd rank in B.Tech. I was awarded GATE fellowship for pursuing M.Tech in Indian Institute of Science, Bangalore, India 1998-2000. I was awarded fellowships for attending the 11th, 12th and 13th International conferences on VLSI Design 1998, 1999 and 2000 conducted at Madras, Goa and Calcutta (India) respectively. Objective: To develop a professional expertise and build an outstanding research career in the areas of high speed, low power digital and mixed signal VLSI with emphasis on wireless telecommunication and ambient intelligence applications. Areas of interests: High speed and low noise CMOS VLSI design, signal integrity including substrate noise, mixed signal VLSI, DFT, communication systems engineering and DSP. Academic qualifications: 1. Masters (M.Tech) in Electronics Design and Technology Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore - 560012, India. Aug 1998 - Jan 2000 Distinction: CGPA 6.4/8, First class, GATE scholarship 1998-2000. Thesis: "Active noise reduction in pilot's headset", sponsored by Defence Bioengineering and Electro medical Laboratory (DEBEL), India. 2. Bachelors (B.Tech) in Electronics Engineering Madras Institute of Technology, Anna University, Chromepet, Chennai - 600044, India. Aug 1995 - May 1998 Distinction: CGPA 9.14/10, First class with Distinction, Rank 3 in University, 3/63 in the class. Thesis: "Implementation of FPGA based GPS baseband processor", sponsored by Indian Space Research Organisation (ISRO). 3. Bachelors (B.Sc) in Physics, University of Madras, India. University of Madras, C. Abdul Hakeem College, Melvisharam - 632509, India. Aug 1992 - May 1995 Distinction: 81.82%, First class with Distinction, Rank 1/41. Professional experience: 1. Research Specialist Mixed Signal and RF Applications (MIRA) group, Design Technology for Integrated Information and Communication Systems division (DESICS), IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium. Http://www.imec.be/design/mixsig & INSYS, Electrical Engineering Department, Katholieke Universiteit, Leuven http://www.esat.kuleuven.ac.be/insys/ Sept 2001 - Present Profile: I am responsible for the analysis and design techniques for reduced switching and substrate noise in mixed signal ICs and low power design. Projects: a. Human++, an ambient intelligence programme with wireless body area network. b. Development of SWAN, a high level substrate noise analysis tool for technologies with high ohmic substrates. 2. IC Design Engineer DSP Product Development (India) Center, Texas Instruments (India) Ltd., Golf View Homes, Wind Tunnel Road, Murugeshpalya, Bangalore - 560017, India. http://www.ti.com/asia/docs/india/dspdesign.html Aug 2000 - Aug 2001 Profile: I was responsible for performing Design For Testability and ATPG for DSPs and broadband communication ICs. Projects: a. Puma, a communications processor IC for Cable Modem applications. b. Taos, a communications processor IC for wireless applications. c. Drishti, a real time DSP emulation system. d. Avalanche-D, a data only version of the broadband communication processor IC. Courses specialised: Graduate level (KU Leuven): Microwave techniques for Microelectronics, Analog Integrated Circuits, Electronic and Opto-electronic System Technology, Numerical Linear Algebra, Object Oriented Programming with Java. Graduate level (IISc): Design for Reliability, Electronic Packaging, Electro magnetic compatibility, Advanced Digital Communication, Microwave Integrated Circuits, Microcomputer system design, Switching theory and VLSI design, Design of Power converters, Analog and Data conversion systems, Designing with PLDs and FPGAs, Basics of VLSI. Undergraduate level (MIT, Anna University): Advanced Digital Signal Processing, Computer Peripherals and Interfacing, Spread Spectrum Theory & Applications, Telematics, Digital System Design Techniques, Communication systems, Digital Communication, Digital Signal Processing. Short courses and professional training: Core subjects: 1. Course on Microwave techniques for microelectronics, IMEC, 2003. 2. Course on Analog IC design, IMEC, 2003. 3. Course on System Identification, IMEC, 2002. EDA tools and methodology: 1. Training on high-level verification of digital systems with Verisity's Specman Elite, TI India, 2001. 2. Training on logic and gate level synthesis with Synopsys, TI India, 2001. 3. Training on FPGA based digital design technology. Design of 10 channel digital radio (RPG and TPG cards) using ACT2 family of ACTel FPGAs, School of Instrumentation and Electronics, Madras Institute of Technology, Chennai, India (For HTL Ltd., Chennai), June - July 1997. Non-technical: 1. Workshops on Fundamentals of communication and Technical writing, IMEC, 2003. 2. Workshop on Technical writing, TI India, 2001. Publications: 1. M. Badaroglu, L. Balasubramanian, K.Tiri, V. Gravot, P. Wambacq, G. Van der Plas, S.Donnay, G. Gielen, H. De Man, "Digital circuit capacitance and switching analysis for ground bounce in ICs with high-ohmic substrates," in IEEE Journal of Solid State Circuits - Special issue on European Solid-State Circuits Conference 2003, 2003. (Invited paper, yet to be published) 2. M. Badaroglu, L. Balasubramanian, K.Tiri, V. Gravot, P. Wambacq, G. Van der Plas, S.Donnay, G. Gielen, H. De Man, "Digital circuit capacitance and switching analysis for ground bounce in ICs with high-ohmic substrates," in Proceedings of the European Solid-State Circuits Conference 2003, pp. 257-260, September 2003. 3. B. Lakshmanan, Sudarshan Dilip Solanki, Dr. M. K. Gunasekaran, Dr. G. Anandarao, Dr. P. P. Krishnapur, "Active noise reduction in pilot's headset" in Journal of Indian Institute of Science. (Submitted) Professional affiliations: 1. IEEE: Member since 2002; Associate Member 2000 - 2002; Student Member 1998 - 2000. Affiliated to IEEE ComSoc, IEEE SSC Society, IEEE MTT Society and IEEE CAS Society. 2. IEE: MIEE since 2002; AMIEE 2000 - 2002; Student Member 1998 - 2000. 3. Engineering Council of UK: CEng since 2000. Language proficiency: English (593/677 in TOEFL 1999), introductory German, introductory Dutch, and Tamil Distinctions and awards: 1. Awarded fellowships for attending the 11th, 12th and 13th International conferences on VLSI Design 1998, 1999 and 2000 conducted at Madras, Goa and Calcutta respectively. 2. Secured 93.37 percentile in Graduate Aptitude Test in Engineering (GATE), 1998 and awarded fellowship for pursuing M.Tech in IISc during 1998-2000. 3. Ranked Third in the University in B.Tech Electronics Engineering, 1998. 4. Assisted in setting up and conducting lab experiments in the Communications and Signal processing lab during B.Tech, 1997-1998. 5. Recipient of Rajam Ramaswamy Award for being the university topper in Control systems engineering, 1997. 6. Recipient of Top 1% in the state (Tamilnadu) award in National Graduate Physics Examination, 1995 conducted by Indian Association of Physics Teachers (IAPT). 7. Distinction and College first in B.Sc. Physics in College, 1995. 8. College first in Part - A Tamil in B.A./B.Sc., 1994. 9. Recipient of Top 10% in the centre award in the National Standard Physics Examination NSPE, 1992 conducted by Indian Association of Physics Teachers (IAPT). 10. School First and District Third in SSLC, 1990. Professional and Academic projects: HUMAN++, IMEC, team of 3 An ambient intelligence programme with wireless body area network 2003 * Presently designing high speed PFDs for low power PLLs in UMC 0.13(m, 1.2V CMOS technology. SWAN, IMEC, team of 5 (http://www.imec.be/design/swan) A high level substrate noise analysis tool for technologies with high ohmic substrates 2001-2003 * Developed a simpler substrate model for noise coupling analysis. * Designed a test chip in UMC 0.18(m, 1.8V CMOS technology for the validation of the substrate model. * The simulations were performed using Spice, Spectre and SeismIC while the parasitic extractions were performed using Dracula, xCalibre, SeismIC and SubstrateStorm. * Wafer probe measurements of this chip were performed to study substrate noise and ground bounce phenomena using Cascade wafer probe system with HP 85107B for model parameter extraction by S-parameter measurement, and with Agilent AGT 81130A signal generator, Tektronix TDS 784C oscilloscope for transient noise measurements. PUMA, TI India, team of 2 A communications processor IC for cable modem applications 2001 * Developed the test specifications and plan. TAOS, TI India, team of 2 A communications processor IC for wireless applications 2001 * Developed the test specifications and plan. 2000-2001 DRISHTI, TI India, team of 2 A real time DSP emulation system * Performed DFT and ATPG based on the methodology and scripts generated by me for a previous project. * Achieved a test coverage of 65% for stuck and Iddq faults for the design of asynchronous nature. AVALANCHE-D, TI India, team of 2 A data only version of the broadband communication processor IC 2000-2001 * Performed DFT and ATPG. * Achieved a test coverage of 90% and 98% for stuck and Iddq faults. * DFT guidelines were documented for use by the design teams. * Chip and block level ATPG for stuck and Iddq faults were performed and design modifications were suggested to the design team for test coverage improvement. * Developed an automated block level and chip level stuck and Iddq ATPG flow using FastScan, FlexTest, Perl and unix shell scripts to integrate DFT in the design flow. * Developed a methodology and an automated process to estimate the preliminary chip level test coverage based on block level coverage. Active Noise Reduction in Pilot's headset, CEDT, IISc, team of 3 Sponsored by Defence Bioengineering and Electro medical Laboratory (DEBEL), India. 1999-2000 * This project aims at the development of indigenous, low cost active noise reduction solutions for aircraft headsets and helmets. ANC is the most effective technique of low frequency noise reduction in enclosed space. Basically, the system operates by inverting the phase of the reference noise and reproduces it to destructively interfere with the primary noise. This results in a localised noise free zone. A laboratory prototype was developed and tested successfully which the sponsors took up for field trials and further development. A peak noise reduction of 22dB was observed with the prototype. Implementation of FPGA based GPS baseband processor, MIT, Anna University, team of 3 Sponsored by Indian Space Research Organisation (ISRO), India. 1997-1998 * This project aims at the implementation of GPS receiver baseband processor. The digitised signal from the GPS receiver front end is fed to the baseband processor. The baseband processor acquires and tracks the carrier and code. It demodulates the signal to recover the 50 bps navigation data. The baseband processor block is implemented using ACTel FPGA. The design entry, logic verification and simulation of the various modules have been carried out with the help of ViewLogic tools. Implementation in VHDL has been done to provide compatibility with future implementations in ASIC. Other projects carried out: Implementation of a Digital PLL in an FPGA, CEDT, IISc, team of 2 2000 Design of a PCB for an IF despreader, CEDT, IISc, team of 2 1999 Design and assembly of a PCB for Humidity and temperature controller using SMDs, CEDT, IISc, team of 2 1999 Implementation of Task switch in Pentium II processor working in real or protected mode, CEDT, IISc, team of 2 1999 Design and implementation of a DC-DC converter (5V, 500A SMPS), CEDT, IISc team of 3 1999 Design and Implementation of a high speed PN sequence generator in 1.2(m, 5V CMOS process using MAGIC layout editor, CEDT, IISc, team of 2 1999 Design and Implementation of a 29 bit DCO using PLDs (CY375I), CEDT, IISc, team of 2 1998 Implementing TSR programs in C and X86 assembly code, MIT, AU, team of 2 1998 AR modelling of speech process in MATLAB, MIT, AU, team of 3 1998 Implementation of asynchronous event driven logic & micropipeline using FPGAs, MIT, AU, team of 4 1997 Implementation of a function generator using XR8038, MIT, AU, team of 2 1997 Keyboard & monitor interface using ACTel FPGAs, MIT, AU, team of 2 Sponsored by Signals and Systems India Private Ltd., Chennai, India. 1997 * This controller FPGA is a part of their product, a hand held computer for field applications, India's first such product in commercial market. Digital Oscilloscope with 10 x 10 LED matrix display, MIT, AU 1997 Design and implementation of Digital Capacitance Meter, MIT, AU, team of 4 1997 Implementation of ECG simulator using 8031 microcontroller, MIT, AU, team of 2 1996 Digital Speech generation using SP0256AL2 and 8085, MIT, AU, team of 2 1996 Digital stop clock, CAHC 1993 AM transmitter using single transistor and AM receiver, CAHC 1990 & 1993 EDA tools: Substrate coupling analysis - Cadence's SubstrateStorm, SeismIC, SCA Parasitic extraction - xCalibre, Dracula, MAGIC layout extractor Simulation - Cadence Spectre, HSpice, SPICE3, IRSIM, PSpice A/D, OrCAD Layout - Cadence Virtuoso layout editor, MAGIC layout editor Synthesis - Synopsys' Design Analyzer, Design Compiler Design for Testability - MGC's DFT Advisor, FastScan, FlexTest, BSDArchitect PLD & FPGA - Actel Designer Series with Viewlogic's Workview office suite, Cypress's WARP VHDL compiler and simulator Verification - Verisity's Specman Elite HDL - VHDL, Verilog HDL RF & Microwave simulation - HP-HFSS, HP-ADS, WinSmith PCB design - OrCAD, CADSTAR, Protel Reliability analysis - Relex's Reliability Digital filter design - DFDP High-level design & analysis - Matlab, Maple, Mathcad, Mathematica Scripting languages - PERL, Unix Shell programming Assembly languages - 8085, 8086, 80386, Pentium II, 8051,ADSP 210X OS - DOS, Unix (HP and Sun Solaris), Windows 95/98/NT High level languages - BASIC, FORTRAN, C, C++, Java Extra & co-curricular activities: 1. Member of ROSE, a non-governmental organisation for the development of primary education in developing countries, since 2003. 2. Member of the administrative committee of Indian Students Association, Leuven (ISAL), Belgium during 2001-2002 and served as the administrator for the homepage of ISAL during 2001-2003. 3. Scored 1960 (out of 2400) in computerised GRE (June 2000) and 593 (677) in paper-based TOEFL (Nov 1999). 4. Programme co-ordinator in MIT Computer Club during 1996-'97. 5. Secured III prize in the district level Physics Exhibition conducted by Sacred Hearts College, Thirupathur, 1994. 6. Recipient of Tamilnadu Government Scholarship for outstanding NCC cadets, 1994. 7. Recipient of NCC National Cadet Welfare Society Scholarship, 1994. 8. College Physics Association Secretary in CAH College, Melvisharam during 1994-'95. 9. College Tamil Literary Association secretary during 1993-'94 and co-ordinator for the conduct of Muthamizh vizha, 1994. 10. An active cadet of NCC in college during 1992-'95. Held the ranks of Corporal, Sergeant, and Company Under Officer Passed B Certificate with B Grade (1994); C Certificate with A Grade (1995) and ranked first in the Battalion of 10 TN Bn NCC, Vellore. Attended annual training camps; 1 National Integration Camp at Kottiyam, Quilon; 1 Army attachment camp at MRC, Wellington. 11. An active cadet in Bharath Scouts and Guides during 1988-'90. Hobbies: Music, cricket and astronomy. Personal details: Unmarried, Indian national, born on 31 July 1975. Permanent address: "PADMARAM NIVAS," 276, Lenin Street, Belliyappa Nagar, Walajapet - 632513, Vellore District, Tamilnadu, India. Phone: +91-4172-232235 References: 1. Prof. Dr. Ir. Georges Gielen, MICAS, ESAT, Katholieke Universiteit of Leuven (KUL), 3001 Leuven, Belgium. Phone: +32-16-321047 Email: georges.gielen@esat.kuleuven.ac.be 2. Dr. Rubin Parekhji, Group Member Technical Staff, DSP Product Development India Center, Texas Instruments India Ltd, Corporate Block, Diamond District, Kodihalli, Airport Road, Bangalore - 560008, India. Phone: +91-80-5099849 Fax: +91-80-5298519 E-mail: parekhji@ti.com 3. Dr.M. K. Gunasekaran, Principal Research Scientist, Centre for Electronics Design and Technology, Indian Institute of Science, C. V. Raman Avenue, Bangalore - 560012, India. Phone: +91-80-3600810 Fax: +91-80-3600808 E-mail: mkguna@cedt.iisc.ernet.in 4. Dr. P. V. Ramakrishna, Assistant Professor, School of Electronics and Communication Engineering, College of Engineering (CEG), Anna University, Guindy, Chennai - 600025, India. Phone: +91-44-22350563 E-mail: pvramakrishna@mitindia.edu 5. Mr. Kuruvilla Varghese, Senior Scientific Officer, Centre for Electronics Design and Technology, Indian Institute of Science, C. V. Raman Avenue, Bangalore - 560012, India. Phone: +91-80-3600810 Fax: +91-80-3600808 E-mail: edkuru@cedt.iisc.ernet.in