Some informations about the Webpal hardware

Schematics

This schematic has been took down by the actual board, with a bit of guesses and a lot of continuity checking.
The Webpal has been built in two slighty different hardware versions.
The schematic below refers to the PWB-117A Ver.01, the only one I own. The other version uses a different Super-I/O controller, a FDC37C666 instead of the FDC37C665.
If you have access to the other version, please let me know the differences, so I can update the schematics to include both versions.

Update 10 jan 2003
   Placed online the sources and the libraries too. Download them from here.

Data sheets

Some pointers to the relevant data sheets:

PS7500:

PS7500 Development Kit: Peripherals:

Serial ports

The serial ports are tied to the J10 and J11 connectors, at TTL (well, CMOS actually) levels. To connect them to a real serial port, you need a level translator (e.g.: a MAX232).
Some notes about the serial ports: There's no information about the IR/Smart card uP, beside the obvious: is a Flash variant of the venerable 8051. I'll give a try to see whether the code has been protected or not. Could be nice to have access to the smart card port, although I see no immediate use (someone is using smart cards?).

Clocks

The clocks for the CPU are made using a Chrontel CH9294G clock syntesizer. The CH9294G provides three outputs: one is fixed at 14.31818 MHz and is used only to feed the CH7001 NTSL/PAL encoder, while the other two are frequency-programmable, strapping some pins to ground. The first programmable output is used to provide the CPU clock, while the other one feeds the video section (pixel clock). Both programming pins sets are hardwired to provide fixed frequencies (read on).

Video clock

The video clock is set at 25.175 MHz and gives a plain vanilla 640*480 @ 60 Hz VGA video output (800 pixel total count =~ 31.5 KHz =~ 2*NTSC line).
Tweaking the frequency pins of the CH9294G is possible to generate several higher frequencies, so should be possible obtain some more interesting resolutions (at least an 800*600 @ 75 Hz). The available frequencies are: 25.175, 28.32, 31.50, 36.00, 40.00, 44.90, 50.00, 65.00, 72.00, 75.00, 77.00, 80.00, 94.50, 110.00, 120.00 and 130.00 MHz.
The video section of the PS7500 accepts frequencies up to 120 MHz.
Changing the CH9294G pins is the simplest way to speed up the video circuitry, although isn't software controllable (unless you wire the frequency control pins to some port).
Here's a list of possible scan rates (not tried, just a guess): 
Resolution | Vert.f (Hz) | Hor.f (KHz) | HTotal |Dot clock (MHz)
-----------+-------------+-------------+--------+---------------
 640 x 480 |     60 NTSC |     31.5    |   800  |  25.175 LLLL (default)
 640 x 480 |     50 PAL  |    ~31.25   |   806  |  25.175 LLLL (default)
 720 x 480 |     60 NTSC |     31.5    |   900  |  28.32  
 720 x 576 |     50 PAL  |    ~31.25   |   906  |  28.32  
 640 x 480 |     72      |     36.5    |   864  |  31.5   HLHH
 640 x 480 |     75      |     37.5    |   840  |  31.5   HLHH
 640 x 480 |     85      |     31.5    |   832  |  36.00  LHHL
 800 x 600 |     72      |     48      |  1040  |  50.00  LHLL
 800 x 600 |     85      |     55.84   |  1160  |  65.00  HHLH
1024 x 768 |     72      |     ????    |  ????  |  80.00  HLHL
1024 x 768 |     85      |     70.24   |  1345  |  94.50  HHHH
The NTSC/PAL outputs are useful only if the video card outputs a signal with an horizontal frequency exactly doubled respect to the TV-horizontal frequency: 31.5 KHz for NTSC and 31.25KHz for PAL. Thus the upper TV-able resolution should be 720*480 @ 60 Hz or 720*576 @ 50 Hz.
The encoded video outputs are resampled by the CH7001, so the actual pixel rate (and thus the pixel "squareness") is just loosely related to the VGA dot clock (i.e.: do not assume an exact 2:1 ratio, see too the unused CH7001's pin UNDERSCAN).

The PS7500 supports a video PLL circuitry too, but no hardware has been fitted in the Webpal (nothing magic, just a 74AC04, a transistor and a couple of passives: see Appendix E in the PS7500 datasheet for the details).

CPU Clock

The PS7500 can operate with different frequencies for the CPU, the I/O and the MEMory. According to the datasheet, the maximum frequencies are: 40 MHz for CPU and 32 MHz for I/O and memory.
Every input can be divided by 2 with an internal software selectable prescaler (at reset the divider is -of course- enabled), thus you can feed up to 80 MHz and 64 MHz, respectively.
The Webpal clock chip feeds to the PS7500 a neat 80 MHz, so the prescaler must be leaved on. Oddly enough, the Webpal hardware clocks everything at 80 (40) MHz, overclocking the I/O and memory sections by a neat 25%! Because of this, the divided signals outputs are shifted up accordingly:
CLK2 is 2.5 MHz
CLK8 is 10.0 MHz
CLK16 is 20.0 MHz

Audio DAC Clock

The clock for the audio DAC is provided by a separate oscillator, running at 22.1184 MHz. The frequency is wrong (should be 22.5792 or 11.2896 MHz, for a 44.100 KHz sampling rate, oversampled 512x and 256x, respectively), so the played audio is about a 2% slower :-(.

NTSC/PAL Video encoder

The CH7001 video encoder provides the composite & S-Video outputs. The encoder expects, as input, an horizontal video frequency exactly doubled respect the output horizontal frequency (i.e.: input=31.5KHz, output 15.75KHz for NTSC). The vertical frequency must be the actual output frequency (60 Hz for NTSC).
The video input signal is fully resampled and filtered by the encoder. The NTSC/PAL interlaced fields are made up by the encoder: as input you must provide a normal not-interlaced VGA field.

The IOP[0..7] pins of the PS7500 are connected to the encoder control lines. Every setting controlled by these pins is related to the composite video & S-Video output only, not the VGA out.

IOP 0UP The video output can be centered pressing several times (!) the button inputs connected to these four pins.
IOP 1DOWN
IOP 2LEFT
IOP 3RIGHT
IOP 4NTSC/-PAL This pin selects the encoding standard: a high level is NTSC, low is PAL. Is up to you provide appropriate frequencies to the video inputs (60 or 50 Hz).
IOP 5Power down IOP5 controls the power down mode: pulling the pin low shuts down the encoder, sparing something around 330 mA (in other words, you cut the board power consumption by almost an half!).
IOP 6MS 1 These two pins are used to select one of four possible anti-flicker vertical filter modes.
IOP 7MS 0

Note: the pin 37 (PD0) has a capacitor connected to Vcc, while according to the datasheet could be left open. Maybe the CH7001 and the CH7001C (the only one datasheet I'm been able to find around) are slighty different beasts, and here the pin 37 has a different function (i.e.: not power down).

DRAM SIMM

The RA11 address pin on the CLPS7500 is not wired to the RAM SIMM slot (is left floating on the SIMM side), so is possible to address up to 2^22 words/bank only (i.e. 16 Mbyte/bank).

Without modifications, you can fit a single bank (aka single sided) module with 2K refresh up to 16 MB or a double sided module up to 32 MB. Wiring the missing address (see http://www.luban.org/Webpal for details & pictures) allows to use single sided SIMMs (w/4K refresh) up to 64 MB, or 128 MB for the double sided version.
The PS7500 has two more (unused) DRAM chip selects, so is theorically possible to fit a maximum of 256 MB (besides the missing socket).

IDE Slot

As you can see in the schematic, the D7 pin of the IDE connector is (wrongly) tied to the pin 11 of U2, so writing to the IDE interface causes a contention between the FDC37C665 and the buffer (which has the input open!). As workaround, lift up the pin 11 (if you hate having floating CMOS inputs around, feel free to provide a pullup/pulldown for both pins, 9 and 11 (and no, you cannot tie the pin directly to GND, because the buffer is bidirectional)).

ISA Bus Slot

The ISA bus slot is decoded by the EASCS signal (physical address 0x08000000...0X0FFFFFFF).
Some notes:
A lot of pins normally supposed to be signals coming from the motherboard and going to the card are left unconnected. This could cause several intermittent problems using cards with CMOS inputs. If you are experiencing this kind of problems, try to pull-up (or down, as appropriate, let's say 10K) the floating card's inputs. In detail, there's absolutely nothing connected to the DMA and to the MEMRD/MEMWR pins: forget to use any NIC card requiring DMA or memory mapped access.
The only interrupt pin connected to the slot is the IRQ3 (wired to the level-sensitive (active high) INT7 pin).

Some links...


e-mail: WMLMBRYXZFIX at spammotel dot com

Last update: 2003/06/24