/*-----------------------------------------------------------------------------
Paul Horne, Steven D. Hurt, and Thomas McNabb
CSE 341, Professor Kris Schindler
Part III
April 24, 2001

Modified from "Four Bit Carry-Look-Ahead Adder," Page 130, Mano and Kime, 
as modified into an eight bit adder and as translated by us into Verilog circuit design language.
-----------------------------------------------------------------------------*/

module part3();  /*eightBitCarryLookAheadAdder*/

/* Declare data types of inputs (a,b,cIn) and outputs (s, c_out)*/
reg[3:0] a,b;
reg c_In;
wire[3:0] s;
wire c_Out;

/* The following variables are defined as parameter for*/
/* eightBitLookahead code  */

/* Instantiate a four bit adder twice*/
adder FAO(a[0],b[0],a[1],b[1],a[2],b[2],
	a[3],b[3],c_In,s[0],s[1],s[2],s[3],c_Out);

	/*instead of cIn, since I set it to zero later, I could*/
	/*write 1'b0*/

/* We will test 1 Carry Lookahead Adder for now
adder FAO(a[4],b[4],a[5],b[5],a[6],b[6],
	a[7],b[7],c4,p_out,g_out,s[4],s[5],s[6],s[7]);
*/

/* eight bit carry lookahead code:  */


initial begin
/*  Monitor value of variables at all instants. Display result */
/*  whenever there is a change. */
$monitor ($time, "a=%b, b=%b, c_In=%b, s=%b, c_Out=%b, ", a, b, c_In,
s, 
c_Out);

/* Set inputs and display time */
a=0; b=0; c_In=0;
#100 $display ($time);

#900 a = 4; b = 7;
#100 $display ($time);

/*
#900 a = 59; b = -10;
#100 $display ($time);

#900 a = -142; b = 39;
#100 $display ($time);

#900 a = 92; b = -92;
#100 $display ($time);

#900 a = 100; b = -174;
#100 $display ($time);
*/

end
endmodule

module adder (A0, B0, A1, B1, A2, B2, A3, B3, CIN, sum0, sum1, sum2, 
sum3, COUT);

/* Declare inputs and outputs */
input A0,B0,A1,B1,A2,B2,A3,B3,CIN;
output sum0,sum1,sum2,sum3,COUT;

PFA FAO(p0,g0,A0,B0);
PFA FAO(p1,g1,A1,B1);
PFA FAO(p2,g2,A2,B2);
PFA FAO(p3,g3,A3,B3);

carryLookAhead FAO(c1,c2,c3,p0,p1,p2,p3,g0,g1,g2,g3,CIN,COUT);

PFB FAO(sum1,p0,C0);
PFB FAO(sum2,p1,c1);
PFB FA0(sum3,p2,c2);
PFB FAO(sum4,p3,c3);
endmodule

module carryLookAhead(C1,C2,C3,P0,P1,P2,P3,G0,G1,G2,G3,C0,C4);
parameter delay0 = 1, delay1=2;
input P0,P1,P2,P3,G0,G1,G2,G3,C0;
output C1,C2,C3,C4;
and /*#delay0*/ (x1,P0,C0), (x2,P1,G0), (x3,P1,P0,C0), (x4,p2,G1), 
	(x5,P2,P1,G0), (x6,P2,P1,P0,C0), (zOut,P3,P2,P1,P0,C0), 
	(x7,P3,G2), (x8,P3,P2,G1), (x9,P3,P2,P1,G0);
or /*#delay1*/ (C1,G0,x1), (C2,G1,x2,x3), (C3,G2,x4,x5,x6), 
	(C4,G3,zOut,x7,x8,x9);
endmodule

module PFA (p0,g0,aIn,bIn);
	input aIn, bIn;
	output p0, g0;	
/* CIRCUIT */	
	and (g0,aIn,bIn);
	xor (p0,aIn,bIn);
endmodule
	
module PFB (sum,p0,cIn);
	parameter delay = 2;
	input p0,cIn;
	output sum;
	xor /*#delay*/ (sum,p0,cIn);
endmodule

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