Monolithic
mixed-mode implementation of sum-of-product arrays for performing
binary morphological image processing
- Spencer, R.G.; Sanchez-Sinencio, E.
Dept. of Electr. Eng., Texas A&M; Univ., College Station, TX, USA
This paper appears in: Circuits and Systems, 1997.
ISCAS '97., Proceedings of 1997 IEEE International Symposium on
On page(s): 1421 - 1424 vol.2
9-12 June 1997
Hong Kong
1997
Volume: 2
ISBN: 0-7803-3583-X
IEEE Catalog Number: 97CH35987
Number of Pages: 4 vol. lxvi+2832
References Cited: 3
INSPEC Accession Number: 5745010
Abstract:
This paper presents a monolithic mixed-mode implementation of
sum-of-product arrays that are capable of performing morphological
image processing in silicon. The digital equations of the two basic
morphological operations, erosion and dilation, are rewritten in a
local, mixed-mode form to facilitate hardware implementation and
results are shown for a 3/spl times/3 selective element array
fabricated in silicon.
Index Terms:
mixed analogue-digital integrated circuits; mathematical
morphology; image processing equipment; image coding; silicon;
elemental semiconductors; mixed-mode implementation; sum-of-product
arrays; binary morphological image processing; digital equations;
erosion; dilation; hardware implementation; selective element array