Hemant Savla
Phone and E-mail Address
(608)358-0712
savla@cae.wisc.edu
Permanent Address
2104 University Avenue, Apt #1,
Madison, WI, ZIP 53726.
OBJECTIVE:- Seeking a permanent position in research and development of RF/Analog VLSI circuits design.
EDUCATION:-
University of Wisconsin-Madison, WI
M.S., Electrical and Computer Engineering, Dec 2003
Current GPA = 3.74/4
Advisor :- Prof. Charlie Chung-Ping Chen
Thesis :- The Design of a Low Power Transceiver for Bluetooth.
Relevant Courses work: -
- Analog CMOS Integrated Circuit Design
- Applied Communications Systems
- Advanced Communication Circuit Design
- VLSI System Design
- Advanced Computer Architecture
- Advanced Topics in Digital System Testingg
- Digital Engineering Laboratory ( FPGA )
Sardar Patel University, India
B.E., Electronics Engineering, Jan 2001
GPA = 9.42/10, ranked 1st in the class of 80 students Relevant Course work: -
- Embedded System Design and Programming
- Digital Signal Processing
- Process Control Engineering
- Power Electronics.
WORK EXPERIENCE:-
Research Assistant July 2002 - present
University of Wisconsin-Madison, WI (VLSI-EDA group) [http://vlsi.ece.wisc.edu/Projects.htm]
Led a design effort to implement a low power RF/Analog transceiver for Bluetooth technology in TSMC 0.18mm CMOS technology.
Design Engineer Jan 2001 – Dec 2001
Chain Electronics Pvt. Ltd., Gandhinagar, India
- Developed a CNC Drilling Machine capable of drilling 56 holes/second in Printed Circuit Boards. - Designed a low cost Copper Thickness Measuring Meter to measure the thickness of copper foil laminated on the base material of Printed Circuit Boards.
- Supervised the design and manufacturing oof Flexible Printed Circuit Boards.
Summer Intern May 2000 – July 2000
Multispan Instruments Company, Ahmedabad, India
- Developed an In Circuit Programmable digiital temperature controller board with Atmel’s RISC Controller AVR.
ACADEMIC PROJECTS:-
- Designed an RF/Analog Bluetooth Transceivver in TSMC 0.18m CMOS technology. The project involved designing, simulation and layout of LNA, Mixer, OTA-C Filter, Limiter/RSSI, Pipelined ADC, Demodulator, Sigma-Delta DAC, VCO, a Phase Locked Loop (PLL), using Cadence and Agilent’s ADS software. Designed receiver achieves a sensitivity of -80 dBm.
- Led a team of 4 people in implementing a 3D Graphics Processing Unit (GPU) on Xilinx XSV-800 FPGA operating at 12.5 MHz with a resolution of 256 x 480. A 16 bit Float Point 5 stage Pipelined RISC Processor capable of processing more than 1000 vertices/second and a Rasterizer pipeline having a throughput close to 1 pixel / clock cycle were designed. 34% FPGA resource usage.
- Transistor level design, simulation and llayout (in 0.35mm technology) of a 4-Stage Pipelined Programmable Digital Filter with a throughput of 166Msamples/s using Mentor graphics and simulation with Eldo (a spice simulator) shows that the system meets the constraints like delay and area.
- Analog Multiplier and OpAmp Design & Impllementation in 0.5mm CMOS technology using Tanner Tools. An OpAmp with gain of 95dB and a bandwidth of 450Mhz was designed.
- Digital Circuit Testing: - Developed an eefficient test set for a circuit of approx 10,000 gates capable of not only detecting the stuck at faults but also pinpointing the locations of those faults in circuit using Perl scripts.
- Designed a Low Noise Amplifier (LNA) for Bluetooth Transceiver, which provides a gain of 12 dB, for a noise figure (NF) of 2.84dB and an input referred IP3 of +7.39 dBm.
- Designed a Microstrip Patch Antenna for aa 2.4GHz ISM band Transceiver and developed a setup for antenna pattern measurement in an anechoic chamber.
- Designed a Data Acquisition and Control BBoard, which scans and controls the tank temperature of a Hot Air Leveling Machine.
COMPUTER SKILLS:-
CAD Tool
- Extensive experience with
* Mentor Graphics IC design flow (Design Architect, IC station, Calibre, Eldo, Quicksim) and
* Cadence IC design flow (Virtuoso, Diva, Assura, Spectre-RF, Verilog-NC, Virtuoso-XL).
- Extensive experience with Agilent’s ADS, Tanner Tools (L-Edit & T-Spice), Hspice, Matlab, Xilinx foundation, FPGA express, ModelSim, Synopsys’ Design Complier.
Languages
- Proficient in C/C++, Perl and Visual Basiic programming
- VerilogHDL / VHDL / Verilog-A and 8051, 880x86, AVR, MIPS, 8085 Assembly languages
PUBLICATION :-
Hemant Savla, Sachin Garg, Vikas Sharma and Charlie Chung-Ping Chen “A Low Power SoC for Bluetooth Transceiver in 0.18mm CMOS” submitted for publication in Design Automation Conference (DAC), 2004
ACTIVITIES :-
- Member of Hoofer’s Sailing Club
- Ranked 2nd in a Mathematical Contest arraanged by Gujarat University, India.