Phase Locked Loop Design

Fuding Ge
fudingge@yahoo.com
All right reserved



This is the page that I collect PLL materials. It is only for my personal usage.



My PLL Project (PDF File)

Do not click on it if you needn't to download it. It is a large file.
The follwoing are the contents:

Chapter 1 Introduction
1.1 Transfer function between the output phase Fo and the input phase FI
1.2 Values for loop filter components R and C: an example
1.3 Transfer function between phase error Fe and the input phase Fi
1.4 Transfer function between wi and wo, we and wi
1.5 PLL operation ranges
1.6 Stead state phase error
1.7 PLL bandwidth and stability analysis
1.8 Noise transfer functions

Chapter 2. PLL function blocks design
2.1 Project specifications

2.2 PFD design
2.3 Charge pump design
2.4 VCO design
VCO circuit design
VCO Phase noise simulation
2.5 Loop filter design
2.6 Frequency divider design

Chapter 3. PLL simulation results
3.1 Pull-in process
3.2 Frequency step response
3.3 Phase step response
3.4 Noise simulation
3.4.1 Fourer analysis
3.4.2 Cycle-to-cycle jitter simulation

Appendix
Notes about Laplace transform
MOSFET model used in this project



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For a complete design, PLL normall need some Auxiliary Circuits (Not implemented in this project):



PLL Modeling with Verilog-A

Transistor level simulation of PLL is very time consuming. At the initial design stage, we need to know some parameters, for example the bandwidth of the PLL, to see if the PLL meet the requirements (for example lock time) or not. At this stage, a modeling enable fast simulation is very useful.

Another important advantage of PLL modeling is the chip (or system) level simulation. For example PLL is just a function block of a chip. At this level simulation, we do not want the transistor level simulation of the PLL, or even worse, with the transistor level PLL, the chip simulation may never be done because the extreme long time simulation.

The models also enable the top-down design methodology.

The following are some Verilog-A modeling of the PLL. You can download them and use them. All models have been tested using Cadence Analog Artist Spectre simulation tools. Any questions, feedbacks, please email me. Thanks.



ASU PLL Course Materilas

Arizona State University EEE598(E) ST: PHASE-LOCKED LOOP SYSTEMS AND CIRCUITS:




Some General PLL Notes



Have Fun with PLL !!!

Have fun! The following is a dynamic calculator to calculte the low-pass filter values for a given phase magin for the 3rd order system.

Here is a dynamic program for low pass filter design for PLL





PLL Applications
  1. Delta Sigma Frequency Syntesizer
  2. Cascading PLLs Notes

You can contact me by send email to fudingge@yahoo.com

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This page was last updated at Jan. 27, 2004