Data converter design was my first "research" area in the analog, mixed signal IC design field.

Performance

DC (static) performance

• Resolution
• Offset (in LSB)
• Gain Error (in LSB)
• INL (aka Relative Accuracy) (in LSB)
• DNL

AC (dynamic) Performance

• SNR:
  • Quantization noise V_Q=V_LSB/Sqrt(12)
  • Random signal uniformaly distributed between 0 and Vref has a SNR=20log(Vin(rms)/V_Q(rms))=20log( Vref/sqrt(12))/V_LSB/sqrt(12) )=20log(2²)=60.2N dB
  • Ideal case (only quantization noise), for sinusoidal waveform between 0 and Vref: SNR=20log( (Vref/(2*sqrt (2))/V_LSB/sqrt(12)=6.02N+1.76 dB
  • DNL in the range of ± 0.5 LSB can reduce the SNR by 3 dB (see I.E Opris talk).
  • If we assume the thermal noise equal to quantization noise, then the SNR will be reduced by another 3 dB.
• Sinal to (noise plus distortion) (SINAD)
• Total Hamonic Distortion (THD)
• Inter-modulation distortion (IMD)
• Spurious-Free Dynamic Range (SFDR): ideal maximum is 9.03N+6 dB (around 9N dB)
• Full power bandwidth
• Small Signal Bandwidth/Effective Resolution Bandwidth (ERBW)

Other Performance Parameters

• Convertion rate
• Effective nunmber of bits

ADC Architecture

Nyquist-Rate ADC

1. Integrating ADC
   • Dual-slope
   • Quad-slope
2. Successive-Approximation Register (SAR) ADC (low power !)
   

   
   

   • 8-16 bit resolution, up to 5 Msps
   • Binary search
3. Algorithmic (Cyclic) ADC
4. Flash (Parallel) ADC
5. Two-step ADC
6. Interpolating ADC
7. Folding ADC
8. Pipeline ADC
9. Time-Interleaved ADC

Oversampling/Delta-Sigma ADC

• Discrete-Time Delta-Sigma ADC
• Continuous-Time Delta-Sigma ADC

Nonideal Effects

• Sampling and Hold Circuit
  • KT/C noise: Minimum sampling capacitance
  • Finite on resistance of the switch: limitted bandwidth
  • Input voltage dependence of the on resistance DR: Distortion
    • HD µ fin*DR*C
    • Use well designed CMOS switch so that the on resistance is less sensitive to input voltage
    • Clock boosting
  • Input voltage dependence of the sampling capacitance DC: Distortion
    HD=fin*DC*R
  • Switch charge injection
    • CMOS Switch with dummy
    • Bottom Plate Sampling (early clock)
  • Clock jitter (aperture uncertaintity)
  • Hold mode feedthrough and droop
• clock feed through
• finite decision-making response time limitted speed

ADC Building Blocks Design

• Opamp Design
  • Gain
  • Bandwidth
• Comparator Design Requirement
  • Offset (need << 1.0 LSB?)
  Comparator Test
  • over-drive test

Signal Code Type

• Sign magnitude
• 1's complementary
• Offset binary
• 2's complementary

ADC Tests

• INL/DNL
  • Histogram: Apply a signal with known distibution and analyze digital code distribution at ADC output
  • code boundary servo: Adjust voltage source to find exact code trip points
• Lynium LLC

ADC Case Study

SAR ADC: 8 bit MAX1117, power consumption: 175 uA @ 1000Ksps and Vdd=3.0V; INL < ± 1 LSB;

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15-b pipelined CMOS Floating-Point A/D Converter:

Normally a switched-capacitor pipelined ADC can achieve a maximum resolution of 10 bits without calibration. But with the floating point architecture, it can reach 15 bits resolution. More please read this IEEE JSSC paper "A 15-b Pipelined CMOS Floating-Point A/D Converterby"by D.U. Thompson and B.A. Wooley at Stanford University. Its sampling rate is 20MS/s, peak SNDR: 60 dB, dynamic range: 90 dB, power supply: 5V analog,4.5V digital, power dissipation: 380 mV in 0.5um triple-metal CMOS with linear poly/Nwell caps tonology and occupy are of 4.3 mm X 3.2 mm (input range is 0.8Vpp, 1.8V). The main problem with this technique is the offset, gain and timing mismatch between channels.

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High speed ADC (for example date convertion rate > 100 MHz)

Time-interleaved architecture may be the natural and best choice. What is time-interleaved structure? It is kind of pipeline of an indivadual ADC array. The individual ADC itself could be pipeline structure too. You can think of this structure as parallel of ADCs operating at the same frequency but with even spaced phase clock signals. With this technique, the research group at UC Davis (Stephen H. Lewis) achieved a 7b 450MSample/s 50mW ADC with area of 0.3mm^2 using 0.18 CMOS process.

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Digital to Analog Converter (DAC)

DAC Architecture

• R-2R:
• Segmented DAC

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Data Converter Modeling

VerilogA Models:

• 8-bit ADC
• An 8-bit ideal DAC. I used this model to transform the results of an 8-bit ADC back to analog signals so that I can measure INL, DNL, THD etc.
• A VerilogA model to measure the DNL of ADC
• A VerilogA model to measure the INL of ADC
• A VerilogA model to measure the DNL of DAC
• A VerilogA model to measure the INL of DAC

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I have designed a charge-redistribution ADC. Here is the write-up of the charge redistribution ADC.

• How to characterizing the amplifier using Cadence Analog Artist? Here is a presentation slides from Cadence

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References

1. Boris Murmann, Bernhard E. Boser, "Digitally Assisted Pipeline ADCs : Theory and Implementation", Kulwer 2004
2. Stanford University EE315: VLSI Data converter class lecture notes, Boris Murmann/Bruce Wooley, http://eeclass.stanford.edu/ee315/
3. UC Berlely EE247 Analog-Digital Interfaces in VLSI Technology class notes, https://www-inst.eecs.berkeley.edu/~ee247/
4. Ion Opris "Challenges in A/D design and practical understanding of their specifications", April 17th, 2003: IEEE Santa Clara Valley (SCV) Solid State Circuits Society talk

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This page was last updated at April, 2005.