DAVID CHUNG

466 Harvard Drive

URL: http://www.oocities.org/david_t_chung

OBJECTIVE

A position as a senior leading engineer where my experiences on VLSI / SOC / ASIC in the area such as digital video; digital audio; digital communication; avionic applications, my education, and my personal capabilities would be of value.

PROFESSIONAL AND TECHNICAL HIGHLIGHTS

· Years experience of working on avionic or flight instrument implementation especially to using current technology to replace obsolete IC devices; completing DO254 compliant requirements, and pass FAA and TSAA certification required documents.

· Years of being a team player in big corporations or private start-up with extensive hands on experiences in designing micro processor based digital image processing IC, digital controller IC, and digital signal processing ASIC, analog to digital conversion ASIC used in multimedia, communication, and avionic applications.

PROFESSIONAL EXPERIENCE

Jan 2006 - Current

Rogerson Kratos Corporation, Pasadena, California

Senior Hardware Design Engineer

· As a leading ASIC designer worked on the ASIC and FPGA designs for the CPU board used in company’s Electronic Flight Instrument System (EFIS) and Integrated Instrument Display System (IIDS), Job function including using Verilog HDL, Synopsys synthesis, ModelSim digital simulation and Matlab simulation, as well as using OrCad to design PC board.

· Responsible to maintain the product line of 10 different avionic instruments (EFIS, IIDS, DU, DAU) which required to have new ASIC designed by using current available CPLD or FPGA technologies to replace obsolete ASIC devices, help company to reopen the production line and ship the products to customers and make company to maintain multi-million dollars profit with this new custom designed ICs.

· Complete all DO254 compliant documents associated with new ASIC designs and obtained TCCA(Transport Canada Civil Aviation), and FAA certificate for these new ASIC designs.

· As a key ASIC designer working on a quality improvement project of redesigning the existing 15 years old analog I/O board which used in display system to converting synchro analog data to digital data. The analog I/O function will be implemented using Digital signal processing method to replace the old analog circuit, use it to reduce the power consumption; Reduce the number of analog IC on the board by using DSP and increase the integration level in ASIC; All of these will simplify the board manufacture processing and increase the product yield. The new IC under development will integrate all the serial I/O data to parallel data conversion, analog to digital conversion, using DSP to replace analog processing and number system conversion.

Oct 2004 - Dec. 2005

SABTECH Industries, Yorba Linda, CA

Senior Hardware Design Engineer

· Working on a retrofit projects, using Lattice CPLD and Xilinx FPGA design to replace obsolete ASIC parts in the existing product, such as Hawke serial NTDS to VME bus interface board and sustaining NEMIS NTDS Matrix Switching System. The retrofitting of Hawke NTDS to VME bus interface board was completed in 3 months, help the company to reopen the production line and ship the parts to NAVY customers whom have waited for more than one year. Project involved of ABEL code, and VHDL code; using ModelSim for simulation; logic analyzer and scopes for board level and system debugging.

Feb 1997 - April 2004

AVS Technology, Inc., City of Industry, CA

Senior Design Engineer / Director of Engineering

· Completed design of four ICs in Multi-format Video Encoder product line: they are AV1480, AV1488, AV3168, AV3169. These ICs been used in OEM Audio/Video commercial products, with a monthly production shipment of 300k to 500k units to major DVD player manufacturers in Asia, and satellite DVB set-top-box manufacturers in the US.

· Completed design of two ICs in Audio CODEC (16-bit ADC and 24-bit DAC) product line:AV2168, AV2188 used in OEM Audio commercial products

· Designed Power Electronic Metering IC (16-bit ADC and micro-controller interface): AV7755 for electrical instrumentation applications.

· Designed testing vectors for the mass production testing of above devices used in the manufacturing testing

Tools used for these projects are: using Verilog Code, VHDL code; using Matlab for architecture modeling; using Synopsys Design Compiler for synthesis and Prime Time for static timing analysis; post routing timing check; SDF back annotation and verification; using ModelSim for simulation; using logic analyzer and scopes for board level and system debugging.

Dec 1994 - Jan 1997

SAMSUNG Electronics, Los Angeles Design Center, Cypress, CA

Senior Staff Engineer and Project Leader

· Completed designs of two mixed signal video encoders ICs KS0125 and KS0127(S5D2650) for VCD and DVD player applications.

· Studied and was involved in design of QAM modem chip use ARM RISC core.

Tools used for these projects are: using Verilog HDL for RTL and gate level logic simulation; using Matlab for architecture modeling; using Synopsys Design Compiler for synthesis and Prime Time for static timing analysis; post routing timing check; SDF back annotation and verification;

Nov 1985 - Dec 1994

XEROX Corp., Corporate Research and Technology, El Segundo, CA

Principal Member of Engineer Staff / Senior member of Staff Engineer / Member of Engineer Staff

· Performed as a team member or a project leader in designing of 13 different ASIC used in the Xerox laser printing system, ranged from image graphic processing to different variants of bus controllers.

Tools used for these projects are: using Verilog HDL for RTL and gate level logic simulation; using Synopsys Design Compiler for synthesis and static timing analysis; post routing timing check; SDF back annotation and verification; using logic analyzer and scopes for board level and system debugging.

June 1983 - Nov 1985

GigaBit Logic Inc., Newbury Park, CA

Design Engineer

· Design high speed GaAs IC Devices for Cray super computer. Used VAX and PDP-11 for SPICE simulation, Used GE's Calma (now Cadence) for circuit layout, wafer testing, package testing in GHz frequency range.

EDUCATION

· MSEE, University of California, Los Angeles (UCLA), Feb 1985

· BSEE, University of California, Los Angeles (UCLA), Jun 1983

PROFESIONAL ACTIVITIES

· Co-author of the paper presented in the Second International Conference on ASIC: "A Multi-Standard Video Compact Disk Encoder With Built-in on Screen Display" 1996 2nd International Conference on Asic Proceedings page: 100-103 ISBN: 7543909405

· Served as Co-Chair of the session: "CAD technique and Simulation" in the Second International Conference On ASIC, 1996.

· Member of IEEE of USA since 1982

U.S. CITIZENSHIP

Reference available upon request